ST ST10F276E - Precautions and Hints; EBC Idle State; Table 31. Status of the External Bus Interface During EBC Idle State

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UM0404 The external bus interface
8.4.3 Precautions and hints
• The external bus interface is enabled as long as at least one of the BUSCON registers
has its BUSACT bit set.
• PORT1 will output the intra-segment address as long as at least one of the BUSCON
registers selects a de-multiplexed external bus, even for multiplexed bus cycles.
• Not all address areas defined via registers ADDRSELx may overlap each other. The
operation of the EBC will be unpredictable in such a case.
• The address areas defined via registers ADDRSELx may overlap internal address
areas. Internal accesses will be executed in this case.
• For any access to an internal address area the EBC will remain inactive (see EBC Idle
State).
8.5 EBC idle state
When the external bus interface is enabled, but no external access is currently executed,
the EBC is idle. As long as only internal resources (from an architecture point of view) such
as IRAM, GPRs or SFRs are used, the external bus interface does not change (see
Table 31).
Accesses to on-chip X-Peripherals are also controlled by the EBC. However, even though
an X-Peripheral appears like an external peripheral to the controller, the respective
accesses do not generate valid external bus cycles.
Due to timing constraints address and write data of an XBUS cycle are reflected on the
external bus interface (see Table 31). The address mentioned above includes Port1, Port4,
BHE
and ALE which also pulses for an XBUS cycle. The external CS signals on Port6 are
driven inactive (high) because the EBC switches to an internal XCS
signal.
The external control signals (RD
and WR or WRL/WRH if enabled) remain inactive
(high) (see Table 31).
Table 31. Status of the external bus interface during EBC idle state
Pins Internal accesses only XBUS accesses
PORT0 Tristate (floating)
Tristate (floating) for read accesses
XBUS write data for write accesses
PORT1
Last used external address
(if used for the bus interface)
Last used XBUS address
(if used for the bus interface)
Port4
Last used external segment address
(on selected pins)
Last used XBUS segment address
(on selected pins)
Port6
Active external CS
signal corresponding to last
used address
Inactive (high) for selected CS
signals
BHE Level corresponding to last external access Level corresponding to last XBUS access
ALE Inactive (low) Pulses as defined for X-Peripheral
RD Inactive (high) Inactive (high)
WR
/WRL Inactive (high) Inactive (high)
WRH Inactive (high) Inactive (high)