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UM0404 Interrupt and trap functions
Note: The trap service routine must clear the respective trap flag, otherwise a new trap will be
requested after exiting the service routine. Setting a trap request flag by software causes
the same effects as if it had been set by hardware.
The reset functions (hardware, software, watchdog) may be regarded as a type of trap.
Reset functions have the highest system priority (trap priority III).
Class A traps have the second highest priority (Trap Priority II), on the third rank are class B
traps, so a class A trap can interrupt a class B trap. If more than one class A trap occur at a
time, they are prioritized internally, with the NMI trap on the highest priority followed by the
stack overflow trap; the stack underflow trap has the lowest priority.
All class B traps have the same trap priority (Trap Priority I). When several class B traps get
active at a time, the corresponding flags in the TFR register are set and the trap service
routine is entered. Since all class B traps have the same vector, the priority to service
simultaneous class B traps is determined by the software in the trap service routine.
If a class A trap occurs during the execution of a class B trap service routine, class A trap
will be serviced immediately. During the execution of a class A trap service routine, no class
B trap will be serviced until the class A trap service routine is exited with a RETI instruction.
In this case, the occurrence of the class B trap condition is stored in the TFR register, but
the IP value of the instruction which caused this trap is lost.
If an Undefined Opcode trap (class B) occurs simultaneously with an NMI trap (class A),
both the NMI and the UNDOPC flags are set, the IP of the instruction with the undefined
opcode is pushed onto the system stack, but the NMI trap is executed. After return from the
NMI service routine, the IP is popped from the stack and immediately pushed again
because of the pending UNDOPC trap.
5.8.3 External NMI trap
Whenever a high to low transition on the dedicated external NMI pin (Non-Maskable
Interrupt) is detected, the NMI flag in register TFR is set and the CPU will enter the NMI trap
routine. The IP value pushed on the system stack is the address of the instruction following
the one after which normal processing was interrupted by the NMI trap.
Note: The NMI
pin is sampled with every CPU clock cycle to detect transitions.
5.8.4 Stack overflow trap
Whenever the stack pointer is decremented to a value which is less than the value in the
stack overflow register STKOV, the STKOF flag in register TFR is set and the CPU will enter
the stack overflow trap routine. Which IP value will be pushed onto the system stack
depends on which operation caused the decrement of the SP.
STKUF
Stack Underflow Flag
The current stack pointer value exceeds the content of register STKUN.
STKOF
Stack Overflow Flag
The current stack pointer value falls below the content of register STKOV.
NMI
Non Maskable Interrupt Flag
A negative transition (falling edge) has been detected on pin NMI
.
Bit Function
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