Interrupt and trap functions UM0404
130/564 DocID13284 Rev 2
priority trap is serviced (see Table 5.1: Interrupt system structure on page 96).
PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and the
CPU level in register PSW is set to the highest possible priority level (level 15), disabling all
interrupts. The CSP is set to code segment zero, if segmentation is enabled. A trap service
routine must be terminated with the RETI instruction.
The nine hardware trap functions of the ST10F276 are divided into two classes:
• Class A traps: These traps share the same trap priority, but have an individual vector
address.
– External Non-Maskable Interrupt (NMI
)
– Stack Overflow
– Stack Underflow trap
• Class B traps: These traps share the same trap priority, and the same vector address.
– Undefined Opcode
– MAC Interruption
– Protection Fault
– Illegal Word Operand Access
– Illegal Instruction Access
– Illegal External Bus Access
The bit-addressable Trap Flag Register (TFR) allows a trap service routine to identify the
kind of trap which caused the exception. Each trap function is indicated by a separate
request flag. When a hardware trap occurs, the corresponding request flag in register TFR
is set to '1'.
TFR (FFACh / D6h) SFR Reset Value: 0000h
1514131211109876543210
NMI
STK
OF
STK
UF
-----
UND
OPC
MAC
TRP
--
PRT
FLT
ILL
OPA
ILL
INA
ILL
BUS
RW RW RW RW RW RW RW RW RW
Bit Function
ILLBUS
Illegal External Bus Access Flag
An external access has been attempted with no external bus defined.
ILLINA
Illegal Instruction Access Flag
A branch to an odd address has been attempted.
ILLOPA
Illegal Word Operand Access Flag
A word operand access (read or write) to an odd address has been attempted.
PRTFLT
Protection Fault Flag
A protected instruction with an illegal format has been detected.
MACTRP
MAC Interrupt Flag
The MAC co-processor has generated an interruption.
UNDOPC
Undefined Opcode Flag
The currently decoded instruction has no valid ST10F276 opcode.
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