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UM0404 Memory organization
In order to minimize the use of the EXTR instructions, the ESFR area mostly holds registers
which are required for initialization and mode selection. Wherever possible, registers that
need to be accessed frequently are allocated in the standard SFR area.
Note: The tools are equipped to monitor accesses to the ESFR area and will automatically insert
EXTR instructions, or issue a warning in case of missing or excessive EXTR instructions.
2.4 The on-chip XRAM
The 66 Kbytes of on-chip extension RAM (single port XRAM) is provided as a storage for
data, user stack and code. It is partially located within data page 3 (XRAM1 - 2 Kbytes), and
partially in code segment 15 (XRAM2 - 64 Kbytes).
Both the XRAM modules are connected to the internal XBUS and are accessed like an
external memory in 16-bit de-multiplexed bus mode without wait-state or read/write delay
(31.25 ns access at 64 MHz CPU clock). Byte and word accesses are allowed.
As the XRAM is connected to the internal XBUS it is accessed like external memory,
however, no external bus cycles are executed for these accesses.
XRAM accesses are globally enabled or disabled via bit XPEN in the SYSCON register.
This bit is cleared after reset and may be set via software during the initialization to allow
accesses to the on-chip XRAM. When bit VISIBLE in the SYSCON register is set also,
accesses to the on-chip XRAM are made visible on the external Port pins. Code fetches are
always made on even byte addresses. Any word and byte data read accesses may use the
indirect or long 16-bit addressing modes. There is no short addressing mode for XRAM
operands. Sequential boundary crossing from XRAM to external memory is not supported
and causes erroneous results.
The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then
any access in the address range 00’E000h - 00’E7FFh will be directed to external memory
interface, using the BUSCONx register corresponding to address matching ADDRSELx
register.
The XRAM2 address range is 0F’0000h - 0F’FFFFh if XPEN (bit 2 of SYSCON register),
and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is cleared, then any access
in the address range 0F’0000h - 00’FFFFh will be directed to external memory interface,
using the BUSCONx register corresponding to address matching ADDRSELx register; the
same occurs when bit XPEN is set, but both bits XRAM2EN and XFLASHEN are cleared.
The lower 16 Kbyte portion of XRAM2 (Address range 0F’0000h-0F’3FFFh) represents the
Stand-by RAM, which can be maintained biased through EA
/V
STBY
pin when main supply
V
DD
is turned off. As the XRAM appears like external memory, it cannot be used as system
stack or as register banks. The XRAM is not provided for single bit storage and therefore is
not bit addressable.
MOV T8REL, R1
;This instruction uses 16-bit address to access
;ESFR T8REL. R1 is duplicated and also ;accessible via
the ESFR mode
;(EXTR is not required for this access)
;----- ;------ ;The scope of the EXTR #3 instruction ends here!
MOV T8REL, R1
;This instruction uses 16-bit address, and does
;not require switching
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