DocID13284 Rev 2 33/564
UM0404 Architectural overview
In order to enhance the performance of the device, a set of additional on-chip X-Peripherals
are available on ST10F276 and controlled through dedicated set of registers:
• Two CAN interfaces,
• Two additional Serial Interfaces (XASC and XSSC),
• A I
2
C Serial Interface,
• An additional 4-channel Pulse Width Modulation unit (XPWM),
• A Real Time Clock module.
1.4.1 Peripheral interfaces
The on-chip peripherals generally have two different types of interfaces: an interface to the
CPU and an interface to external hardware. Communication between CPU and peripherals
is performed through Special Function Registers (SFRs) and interrupts. The SFRs serve as
control/status and data registers for the peripherals. Interrupt requests are generated by the
peripherals based on specific events which occur during their operation such as end of task,
new event, or errors.
Specific pins of the parallel ports are used for interfacing with external hardware when an
input or output function has been selected for a peripheral. During this time, the port pins are
controlled by the peripheral (when used as outputs) or by the external hardware which
controls the peripheral (when used as inputs). This is called the ‘alternate (input or output)
function’ of a port pin, in contrast to its function as a general purpose I/O pin.
Similarly, the on-chip X-Peripherals communicate with the CPU through a dedicated set of
registers and dedicated structure of interrupt management system.
1.4.2 Peripheral timing
Internal operation of CPU and peripherals is based on the CPU clock (f
CPU
). The on-chip
oscillator derives the CPU clock from the crystal or from the external clock signal.
The clock signal which is gated to the peripherals is independent from the clock signal which
feeds the CPU. During Idle mode the CPU’s clock is stopped while the peripherals continue
their operation.
When an SFR is written to by software in the same state where it is also to be modified by
the peripheral, the software write operation has priority. Further details on peripheral timing
are included in the specific sections about each peripheral.
1.4.3 Programming hints
Access to SFRs: All SFRs reside in data page 3 of the memory space. The following
addressing mechanisms are used to access the SFRs:
• Indirect or direct addressing with 16-bit (mem) addresses it must be guaranteed that
the used data page pointer (DPP0...DPP3) selects data in memory space page 3.
• accesses via the Peripheral Event Controller (PEC) use the SRCPx and DSTPx
pointers instead of the data page pointers.
• short 8-bit (reg) addresses to the standard SFR area do not use the data page
pointers but directly access the registers within this 512 byte area.
• short 8-bit (reg) addresses to the extended ESFR area require switching to the 512
byte extended SFR area. This is done via the EXTension instructions EXTR, EXTP(R),
EXTS(R).
To Next Page
Loading...
