ST ST10F276E - ST10 Configuration in BSL; Booting Steps

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UM0404 The bootstrap loader
15.2.2 ST10 configuration in BSL
When the ST10F276 has entered BSL mode, the following configuration is automatically set
(values that deviate from the normal reset values, are marked in bold):
Other than after a normal reset the watchdog timer is disabled, so the bootstrap loading
sequence is not time limited. Depending on the selected serial link (UART0 or CAN1), pin
TxD0 or CAN1_TxD is configured as output, so the ST10F276 can return the acknowledge
byte. Even if the internal IFLASH is enabled, no code can be executed out of it.
15.2.3 Booting steps
As Figure 125 shows, booting ST10F276 with the boot loader code occurs in four steps
minimum:
1. The ST10F276 is reset with P0L.4 low.
2. The internal new bootstrap code runs on the ST10 and a first level user code is
downloaded from the external device, via the selected serial link (UART0 or CAN1).
The bootstrap code is contained in the ST10F276 Test-Flash and is automatically run
Watchdog Timer Disabled
Register SYSCON: 0404
H
(1)
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin
level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration.
XPEN bit set for Bootstrap via
; CAN or Alternate Boot Mode
Context Pointer CP: FA00
H
Register STKUN: FC00
H
Stack Pointer SP: FA40
H
Register STKOV: FA00
H
Register BUSCON0: acc. to startup config.
(2)
2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low
during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE
signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.
Register S0CON: 8011
H
Initialized only if Bootstrap via UART
Register S0BG: acc. to ‘00’ byte ; Initialized only if Bootstrap via UART
P3.10 / TXD0: note
(1)
Initialized only if Bootstrap via UART
DP3.10: note
(1)
Initialized only if Bootstrap via UART
CAN1 Status/Control
register:
0000
H
Initialized only if Bootstrap via CAN
CAN1 Bit Timing Register: acc. to ‘0’ frame Initialized only if Bootstrap via CAN
Register XPERCON: 042D
H
XRAM1-2, XFlash, CAN1 and XMISC enabled
Initialized only if Bootstrap via CAN
P4.6 / CAN1_TxD: note
(1)
Initialized only if Bootstrap via CAN
DP4.6: note
(1)
Initialized only if Bootstrap via CAN