DocID13284 Rev 2 207/564
UM0404 The external bus interface
Figure 71. External bus arbitration, (regaining the bus)
Note: The falling BREQ
edge shows the last chance for BREQ to trigger the indicated regain-
sequence. Even if BREQ
is activated earlier the regain-sequence is initiated by HOLD going
high. BREQ
and HOLD are connected via an external arbitration circuitry. Note that HOLD
may also be deactivated without the ST10F276 requesting the bus.
8.7 The XBUS interface
The ST10F276 provides an on-chip interface (the XBUS interface), which allows to connect
integrated costumer / application specific peripherals to the standard controller core.
The XBUS is an internal representation of the external bus interface, it works in the same
way.
The current XBUS interface is prepared to support up to three X-Peripherals: for each
peripheral on the XBUS (X-Peripheral) there is a separate address window controlled by an
XBCON and an XADRS registers.
As an interface to a peripheral in many cases is represented by just a few registers, the
XADRS registers select smaller address windows than the standard ADDRSEL registers.
X-Peripheral accesses provide the same choices as external accesses, so these
peripherals may be byte wide or word wide, with or without a separate address bus.
As the register pairs control integrated peripherals rather than externally connected ones,
they are typically fixed by mask programming rather than being user programmable.
Nevertheless, on ST10F276, the XADRS3 register is available and programmable for the
user. It defines the memory range for XFLASH, Flash Control Registers and XRAM2
accesses.
XADRS3 (F01Ch / 0Eh) ESFR Reset Value: 800Bh
HOLD
HLDA
BREQ
CSx
Other
Signals
1514131211109876543210
RGSAD RGSZ
RW RW
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