DocID13284 Rev 2 37/564
UM0404 Architectural overview
In addition, a specific interrupt request for this capture/compare register is generated. Either
a positive, a negative, or both a positive and a negative external signal transition at the pin
can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare register,
specific actions will be taken, based on the selected compare mode.
1.4.9 Pulse width modulation unit
The Pulse Width Modulation Module can generate up to four PWM output signals using
edge-aligned or centre-aligned PWM. In addition the PWM module can generate PWM burst
signals and single shot outputs.
In Burst Mode two channels can be combined with their output signals ANDed, where one
channel gates the output signal of the other channel. In Single Shot Mode, a single output
pulse is generated (retriggerable) under software control.
Each PWM channel is controlled by an up/down counter with associated reload and
compare registers. The polarity of the PWM output signals may be controlled via the
respective port output latch (combination via EXOR).
The XPWM is an additional 4-channel PWM unit, functionally identical with the standard
PWM. The XPWM is an X-Peripheral (no bit handling) and support 1 interrupt source. The
port line and interrupt handling is slightly different from that of the standard PWM unit.
1.4.10 A/D converter
A 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has
been integrated on-chip for analog signal measurement. An additional eight multiplexed
channels are also available on Port1 with a reduced accuracy.
It uses a successive approximation method. The sample time (for loading the capacitors)
and conversion time is programmable and can be modified for the external circuitry.
Overrun error detection/protection is provided for the conversion result register (ADDAT).
When the result of a previous conversion has not been read from the result register at the
time the next conversion is complete, either an interrupt request is generated, or the next
conversion is suspended, until the previous result has been read.
For applications which require less than 24 analog input channels, the remaining channel
inputs can be used as digital input/output port pins (note that Port5 is input only, while Port1
is input/output).
The A/D converter of the ST10F276 supports four different conversion modes:
• Standard Single Channel conversion mode: the analog level on a specified channel is
sampled once and converted to a digital result.
• Single Channel Continuous mode: the analog level on a specified channel is
repeatedly sampled and converted without software intervention.
• For the Auto Scan mode: the analog levels on a pre-specified number of channels are
sampled and converted in sequence.
• In the Auto Scan Continuous mode: the number of pre-specified channels is repeatedly
sampled and converted.
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