ST ST10F276E - Prioritizing Interrupt & PEC Service Requests; Enabling and Disabling Interrupt Requests; Figure 20. Mapping of PEC Pointers into the IRAM

Interrupt and trap functions UM0404
106/564 DocID13284 Rev 2
The source and destination pointers specify the locations between which the data is to be
moved. A pair of pointers (SRCPx and DSTPx) is associated with each of the eight PEC
channels. These pointers do not reside in specific SFRs, but are mapped into the IRAM of
the ST10F276 just below the bit-addressable area (see Figure 20).
Figure 20. Mapping of PEC pointers into the IRAM
PEC data transfers do not use the data page pointers DPP3...DPP0. The PEC source and
destination pointers are used as 16-bit intra-segment addresses within segment 0, so data
can be transferred between any two locations within the first four data pages 3...0.
The pointer locations for inactive PEC channels may be used for general data storage. Only
the required pointers occupy RAM locations.
Note: If word data transfer is selected for a specific PEC channel (BWT=’0’), the respective source
and destination pointers must both contain a valid word address which points to an even
byte boundary. Otherwise the Illegal Word Access trap will be invoked, when this channel is
used.
5.3 Prioritizing interrupt & PEC service requests
Interrupt and PEC service requests from all sources can be enabled, so they are arbitrated
and serviced (if they win), or they may be disabled, so their requests are disregarded and
not serviced.
5.3.1 Enabling and disabling interrupt requests
This may be done in three ways:
• Control bits allow to switch each individual source “ON” or “OFF”, so it may generate a
request or not. The control bits (xxIE) are located in the respective interrupt control
registers. All interrupt requests may be enabled or disabled generally via bit IEN in
register PSW. This control bit is the “main switch” that selects if requests from any
source are accepted or not.
In order to be arbitrated, both dedicated and global enabled bits of the interrupt source
must be set.
• The Priority Level automatically selects a certain group of interrupt requests that will
be acknowledged, disclosing all other requests. The priority level of the source that
wins the arbitration is compared against the CPU’s current level and only this source is
DSTP7
00’FCFEh
SRCP7
00’FCFC
h
DSTP6
00’FCFAh
SRCP6
00’FCF8h
DSTP5
00’FCF6h
SRCP5
00’FCF4h
DSTP4
00’FCF2h
SRCP4
00’FCF0h
DSTP3
00’FCEEh
SRCP3
00’FCEC
h
DSTP2
00’FCEAh
SRCP2
00’FCE8h
DSTP1
00’FCE6h
SRCP1
00’FCE4h
DSTP0
00’FCE2h
SRCP0
00’FCE0h