ST ST10F276E - General Purpose Registers (Gprs); Table 68. General Purpose Registers (Gprs); Table 69. General Purpose Registers (Gprs) Bit Wise Addressing

Register set UM0404
516/564 DocID13284 Rev 2
26.2 General purpose registers (GPRs)
The GPRs form the register bank that the CPU works with. This register bank may be
located anywhere within the IRAM via the Context Pointer (CP). Due to the addressing
mechanism, GPR banks can only reside within the IRAM. All GPRs are bit-addressable.
The first eight GPRs (R7...R0) may also be accessed byte wise. Other than with SFRs,
writing to a GPR byte does not affect the other byte of the respective GPR. The respective
halves of the byte-accessible registers receive special names:
Table 68. General purpose registers (GPRs)
Name
Physical
address
8-bit
address
Description
Reset
value
R0 (CP) + 0 F0h CPU General Purpose (word) Register R0 UUUUh
R1 (CP) + 2 F1h CPU General Purpose (word) Register R1 UUUUh
R2 (CP) + 4 F2h CPU General Purpose (word) Register R2 UUUUh
R3 (CP) + 6 F3h CPU General Purpose (word) Register R3 UUUUh
R4 (CP) + 8 F4h CPU General Purpose (word) Register R4 UUUUh
R5 (CP) + 10 F5h CPU General Purpose (word) Register R5 UUUUh
R6 (CP) + 12 F6h CPU General Purpose (word) Register R6 UUUUh
R7 (CP) + 14 F7h CPU General Purpose (word) Register R7 UUUUh
R8 (CP) + 16 F8h CPU General Purpose (word) Register R8 UUUUh
R9 (CP) + 18 F9h CPU General Purpose (word) Register R9 UUUUh
R10 (CP) + 20 FAh CPU General Purpose (word) Register R10 UUUUh
R11 (CP) + 22 FBh CPU General Purpose (word) Register R11 UUUUh
R12 (CP) + 24 FCh CPU General Purpose (word) Register R12 UUUUh
R13 (CP) + 26 FDh CPU General Purpose (word) Register R13 UUUUh
R14 (CP) + 28 FEh CPU General Purpose (word) Register R14 UUUUh
R15 (CP) + 30 FFh CPU General Purpose (word) Register R15 UUUUh
Table 69. General purpose registers (GPRs) bit wise addressing
Name
Physical
address
8-bit
address
Description
Reset
value
RL0 (CP) + 0 F0h CPU General Purpose (byte) Register RL0 UUh
RH0 (CP) + 1 F1h CPU General Purpose (byte) Register RH0 UUh
RL1 (CP) + 2 F2h CPU General Purpose (byte) Register RL1 UUh
RH1 (CP) + 3 F3h CPU General Purpose (byte) Register RH1 UUh
RL2 (CP) + 4 F4h CPU General Purpose (byte) Register RL2 UUh
RH2 (CP) + 5 F5h CPU General Purpose (byte) Register RH2 UUh
RL3 (CP) + 6 F6h CPU General Purpose (byte) Register RL3 UUh