ST ST10F276E - Programmable Output Clock Divider

Programmable output clock divider UM0404
514/564 DocID13284 Rev 2
25 Programmable output clock divider
A specific register mapped on the XBUS allows to choose the division factor on the
CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address
range.
Real time clock and power down modeXBUS Reset Value: - - 00h
When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default
the CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN
of register SYSCON, it is possible to program the clock prescaling factor: in this way on
P3.15 a prescaled value of the CPU clock can be output.
When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15
does not output any clock signal, even though XCLKOUTDIV register is programmed.
1514131211109876543210
-------- DIV
RW
Bit Function
DIV
Clock Divider setting
‘00h’: f
CLKOUT
= f
CPU
‘01h’: f
CLKOUT
= f
CPU
/ 2
‘02h’: f
CLKOUT
= f
CPU
/ 3
‘03h’: f
CLKOUT
= f
CPU
/ 4
‘FFh’: f
CLKOUT
= f
CPU
/ 256