ST ST10F276E - Context Switching; Figure 21. Task Status Saved on the System Stack

DocID13284 Rev 2 109/564
UM0404 Interrupt and trap functions
Figure 21. Task status saved on the system stack
The interrupt request flag of the source that is being serviced is cleared. The IP is loaded
with the vector associated with the requesting source (the CSP is cleared in case of
segmentation) and the first instruction of the service routine is fetched from the respective
vector location, which is expected to branch to the service routine itself. The data page
pointers and the context pointer are not affected.
When the interrupt service routine is left (RETI is executed), the status information is
popped from the system stack in the reverse order, taking into account the value of bit
SGTDIS.
5.4.1 Context switching
An interrupt service routine usually saves all the registers it uses on the stack, and restores
them before returning. The more registers a routine uses, the more time is wasted with
saving and restoring. The ST10F276 allows to switch the complete bank of CPU registers
(GPRs) with a single instruction, so the service routine executes within its own, separate
context.
The instruction “SCXT CP, #New_Bank” pushes the content of the context pointer (CP) on
the system stack and loads CP with the immediate value “New_Bank”, which selects a new
register bank. The service routine may now use its “own registers”. This register bank is
preserved, when the service routine terminates its contents are available on the next call.
Before returning (RETI) the previous CP is simply POPped from the system stack, which
returns the registers to the original bank.
Note: The first instruction following the SCXT instruction must not use a GPR.
Resources that are used by the interrupting program must eventually be saved and restored
(the DPPs and the registers of the MUL/DIV unit).
_ _
_ _
_ _
SP
PSW
IP
_ _
PSW
CSP
IP
SP
Low
Addresses
High
Addresses
Status of
Interrupted
Task
SP
a) System stack before
Interrupt Entry
b) System stack after
Interrupt Entry (unsegmented)
b) System stack after
Interrupt Entry (segmented)