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ST ST10F276E - The Multiply; Divide High Register MDH; The Multiply; Divide Low Register MDL

ST ST10F276E
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The central processing unit (CPU) UM0404
78/564 DocID13284 Rev 2
This control mechanism is not triggered, and no stack trap is generated, when:
The stack pointer SP is directly updated via MOV instructions.
The limits of the stack area (STKOV, STKUN) are changed, so that SP is outside of the
new limits.
3.4.13 The multiply / divide high register MDH
This register is a part of the 32-bit multiply/divide register, which is implicitly used by the
CPU, when it performs a multiplication or a division. After a multiplication, this non-bit-
addressable register represents the high order 16 bits of the 32-bit result. For long divisions,
the MDH register must be loaded with the high order 16 bits of the 32-bit dividend before the
division is started. After any division, register MDH represents the 16-bit remainder.
MDH (FE0Ch / 06h) SFR Reset Value: 0000h
Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU)
flag in the Multiply/Divide Control register (MDC) is set to '1'. When a multiplication or
division is interrupted before its completion and when a new multiply or divide operation is to
be performed within the interrupt service routine, register MDH must be saved along with
registers MDL and MDC to avoid erroneous results.
A detailed description of how to use the MDH register for programming multiply and divide
algorithms can be found in Section 27: System programming on page 545.
3.4.14 The multiply / divide low register MDL
This register is a part of the 32-bit multiply/divide register, which is implicitly used by the
CPU, when it performs a multiplication or a division. After a multiplication, this non-bit-
addressable register represents the low order 16 bits of the 32-bit result. For long divisions,
the MDL register must be loaded with the low order 16 bits of the 32-bit dividend before the
division is started. After any division, register MDL represents the 16-bit quotient.
MDL (FE0Eh / 07h) SFR Reset Value: 0000h
1514131211109876543210
mdh
RW
Bit Function
MDH Specifies the high order 16 bits of the 32-bit multiply and divide register MD.
1514131211109876543210
mdl
RW
Bit Function
mdl Specifies the low order 16 bits of the 32-bit multiply and divide register MD.

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