Power reduction modes UM0404
510/564 DocID13284 Rev 2
interface is frozen in order to avoid any kind of data corruption. It is then possible to turn off
the main V
DD
provided that V
STBY
is on.
A dedicated embedded low-power voltage regulator is implemented to generate the internal
low voltage supply (about 1.65V in Stand-by mode) to bias all those circuits that should
remain active: the portion of XRAM (16 Kbytes), the RTC counters and 32 kHz on-chip
oscillator amplifier.
In normal running mode (that is when main V
DD
is on) the V
STBY
pin can be tied to V
SS
during reset to exercise the EA
functionality associated with the same pin: the voltage
supply for the circuitries which are usually biased with V
STBY
(see in particular the 32 kHz
oscillator used in conjunction with Real Time Clock module), is granted by the active main
V
DD
.
It must be noted that Stand-by Mode can generate problems associated with the usage of
different power supplies in CMOS systems; particular attention must be paid when the
ST10F276 I/O lines are interfaced with other external CMOS integrated circuits: if V
DD
of
ST10F276 becomes (for example in Stand-by Mode) lower than the output level forced by
the I/O lines of these external integrated circuits, the ST10F276 could be directly powered
through the inherent diode existing on ST10F276 output driver circuitry. The same is valid
for ST10F276 interfaced to active/inactive communication buses during Stand-by mode:
current injection can be generated through the inherent diode.
Furthermore, the sequence of turning on/off of the different voltage could be critical for the
system (not only for the ST10F276 device). The device Stand-by mode current (I
STBY
) may
vary while V
DD
to V
STBY
(and vice versa) transition occurs: some current flows between V
DD
and V
STBY
pins. System noise on both V
DD
and V
STBY
can contribute to increase this
phenomenon.
24.3.1 Entering stand-by mode
As already said, to enter Stand-by Mode XRAM2EN bit in the XPERCON Register must be
cleared (note that this bit is automatically reset by any kind of RESET event, see Section 23:
System reset on page 472): this allows to freeze immediately the RAM interface, avoiding
any data corruption. As a consequence of a RESET event, the RAM Power Supply is
switched to the internal low-voltage supply V
18SB
(derived from V
STBY
through the low-
power voltage regulator). The RAM interface will remain frozen until the bit XRAM2EN is set
again by software initialization routine (at next exit from main V
DD
Power-On reset
sequence).
Since V
18
is falling down (as a consequence of V
DD
turning off), it can happen that the
XRAM2EN bit is no longer able to guarantee its content (logic “0”), being the XPERCON
Register powered by internal V
18
. This does not generate any problem, because the Stand-
by Mode switching dedicated circuit continues to confirm the RAM interface freezing,
irrespective the XRAM2EN bit content; XRAM2EN bit status is considered again when
internal V
18
comes back over internal stand-by reference V
18SB
.
If internal V
18
becomes lower than internal stand-by reference (V
18SB
) of about 0.3-0.45V
with bit XRAM2EN set, the RAM Supply switching circuit is not active: in case of a
temporary drop on internal V
18
voltage versus internal V
18SB
during normal code execution,
no spurious Stand-by Mode switching can occur (the RAM is not frozen and can still be
accessed).
The ST10F276 Core module, generating the RAM control signals, is powered by internal
V
18
supply; during turning off transient these control signals follow the V
18
, while RAM is
switched to V
18SB
internal reference. It could happen that a high level of RAM write strobe
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