ST ST10F276E - Example of External Network Sizing

Analog / digital converter UM0404
390/564 DocID13284 Rev 2
19.5.4 Example of external network sizing
The following hypothesis are formulated in order to proceed in designing the external
network on A/D Converter input pins:
• Analog Signal Source Bandwidth (f
0
): 10 kHz
• Conversion Rate (f
C
): 25 kHz
• Sampling Time (T
S
): 1µs
• Pin Input Capacitance (C
P1
): 5pF
• Pin Input Routing Capacitance (C
P2
): 1pF
• Sampling Capacitance (C
S
): 4pF
• Maximum Input Current Injection (I
INJ
): 3mA
• Maximum Analog Source Voltage (V
AM)
: 12V
• Analog Source Impedance (R
S
): 100Ω
• Channel Switch Resistance (R
SW
): 500Ω
• Sampling Switch Resistance (R
AD
): 200Ω
1. Supposing to design the filter with the pole exactly at the maximum frequency of the
signal, the time constant of the filter is:
2. Using the relation between C
F
and C
S
and taking some margin (4000 instead of 2048),
it is possible to define C
F
:
3. As a consequence of step 1 and 2, RC can be chosen:
4. Considering the current injection limitation and supposing that the source can go up to
12V, the total series resistance can be defined as:
5. from which is now simple to define the value of R
L
:
6. Now the three element of the external circuit R
F
, C
F
and R
L
are defined. Some
conditions discussed in the previous paragraphs have been used to size the
component, the other must now be verified. The relation which allow to minimize the
R
C
C
F
1
2
πf
0
-------------
15.9μs==
C
F
4000 C
S
⋅ 16nF==
R
F
1
2
πf
0
C
F
---------------------
995Ω 1kΩ≅==
R
S
R
F
R
L
V
AM
I
INJ
------------- 4 k Ω==++
R
L
V
AM
I
INJ
------------- R
F
R
S
2.9kΩ=––=