ST ST10F276E - Table 20. X-Interrupt Detailed Mapping; Figure 24. X-Interrupt Basic Structure

Interrupt and trap functions UM0404
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absence of the possibility to serve the related interrupt request: a periodic polling of the flag
bits may be implemented inside the user application.
Note: The XIRxSEL registers are mapped into the XMiscellaneous area. Therefore they can be
accessed only if the XMISCEN bit is set in XPERCON register and if XPEN bit is set in
SYSCON register.
Figure 24. X-Interrupt basic structure
Table 20 summarizes the mapping of the different interrupt sources which shares the four X-
interrupt vectors. For details on bits inside the XIRxSEL registers, refer to register
description section reported just after the table itself.
Since the XIRxSEL registers are not bit addressable, another pair of registers (a couple for
each XIRxSEL) is provided to allow setting and clearing the bits of XIRxSEL without risking
to overwrite requests coming after reading the register and before writing it. These registers
are described in this section as well.
XIRxSEL[7:0] (x = 0, 1, 2, 3)
XIRxSEL[15:8] (x = 0, 1, 2, 3)
XPxIC.XPxIR (x = 0, 1, 2, 3)
70
15 8
IT Source 7
IT Source 6
IT Source 5
IT Source 4
IT Source 3
IT Source 2
IT Source 1
IT Source 0
Enable[7:0]
Flag[7:0]
Table 20. X-Interrupt detailed mapping
XP0INT XP1INT XP2INT XP3INT
CAN1 Interrupt x x
CAN2 Interrupt x x
I
2
C Receive x x x
I
2
C Transmit xxx
I
2
C Error x
XSSC Receive x x x
XSSC Transmit x x x
XSSC Error x