ST ST10F276E - Figure 98. GPT2 Register CAPREL in Capture-And-Reload Mode; Interrupt Control for GPT2 Timers and CAPREL

The general purpose timer units UM0404
244/564 DocID13284 Rev 2
Figure 98. GPT2 register CAPREL in capture-and-reload mode
9.2.2 Interrupt control for GPT2 timers and CAPREL
When a timer overflows from FFFFh to 0000h (counting up), or when it underflows from
0000h to FFFFh (counting down), its interrupt request flag (T5IR or T6IR) in register TxIC
will be set. Whenever a transition according to the selection in bit-field CI is detected at pin
CAPIN, interrupt request flag CRIR in register CRIC is set. Setting any request flag will
cause an interrupt to the respective timer or CAPREL interrupt vector (T5INT, T6INT or
CRINT) or trigger a PEC service, if the respective interrupt enable bit (T5IE or T6IE in
register TxIC, CRIE in register CRIC) is set. There is an interrupt control register for each of
the two timers and for the CAPREL register.
T5IC (FF66h / B3h) SFR Reset Value: - - 00h
T6IC (FF68h / B4h) SFR Reset Value: - - 00h
Cl
Edge
Select
T5CLR
CAPIN
P3.2
T5SC
Auxiliary Timer T5
CAPREL Register
CRIR
T5IR
Interrupt
Request
Interrupt
Request
Up/Down
Input
Clock
Core Timer T6
T6OTL
T6OUT
P3.1
T6IR
Interrupt
Request
To CAPCOM
Timers
Up/Down
Input
Clock
T6SR T6OE
T0, T1, T7, T8
1514131211109876543210
--------T5IRT5IE ILVL GLVL
RW RW RW RW
1514131211109876543210
--------T6IRT6IE ILVL GLVL
RW RW RW RW