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UM0404 I
2
C interface
If it is a Start then the interface discards the data and waits for the next slave address
on the bus.
• AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
Note: In both cases, SCL line is not held low; however, SDA line can remain low due to possible
«0» bits transmitted last. It is then necessary to release both lines by software.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released
after the transfer of the current byte.
20.3.2 Master mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.
Then the master waits for a write to the I2CDR register with the Slave address, holding the
SCL line low (see Figure 170 - Transfer sequencing EV5).
Slave address transmission
Then the slave address is sent to the SDA line via the internal shift register.
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte including the header sequence causes the
following event:
• The EVF and ADD10 bits are set by hardware with interrupt generation if the ITE bit is
set.
Then the master waits for a read of the I2CSR1 register followed by a write in the I2CDR
register, holding the SCL line low (see Figure 170 - Transfer sequencing EV9).
Then the second address byte is sent by the interface.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set):
• The EVF and ENDAD bits are set by hardware with interrupt generation if the ITE bit is
set.
Then the master waits for a read of the I2CSR1 register followed by a write in the I2CCR
register (for example set PE bit), holding the SCL line low (see Figure 170 - Transfer
sequencing EV6).
Next the master must enter Receiver or Transmitter mode.
Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate
a repeated Start condition and re-send the header sequence with the least significant bit set
(11110xx1).
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