ST ST10F276E - Page 396

I
2
C interface UM0404
396/564 DocID13284 Rev 2
Header matched (10-bit mode only): the interface generates an acknowledge pulse if the
ACK bit is set.
Address not matched: the interface ignores it and waits for another Start condition.
Address matched: the interface generates in sequence:
• Acknowledge pulse if the ACK bit is set.
• EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the I2CSR1 register, holding the SCL line low (see
Figure 170 - Transfer sequencing EV1).
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1).
Slave receiver
Following the address reception and after I2CSR1 register has been read, the slave
receives bytes from the SDA line into the I2CDR register via the internal shift register. After
each byte the interface generates in sequence:
• Acknowledge pulse if the ACK bit is set
• EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the I2CDR register, holding the SCL line low (see
Figure 170 - Transfer sequencing EV2).
Slave transmitter
Following the address reception and after I2CSR1 register has been read, the slave sends
bytes from the I2CDR register to the SDA line via the internal shift register.
The slave waits for a write to the I2CDR register, holding the SCL line low (see Figure 170
- Transfer sequencing EV3).
When the acknowledge pulse is received:
• The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Closing slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets:
• EVF and STOPF bits with an interrupt if the ITE bit is set.
Then the interface waits for a read of the I2CSR2 register (see Figure 170 - Transfer
sequencing EV4).
Error cases
• BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop then the interface discards the data, releases the lines and waits for
another Start condition.