ST ST10F276E - Inseparable Instruction Sequences; Overriding the DPP Addressing Mechanism

DocID13284 Rev 2 555/564
UM0404 System programming
27.8 Inseparable instruction sequences
The instructions of the ST10F276 are very efficient (most instructions execute in one
instruction cycle) and even the multiplication and division are interruptible in order to
minimize the response latency to interrupt requests (internal and external). In many
microcontroller applications this is vital.
Some special occasions, however, require certain code sequences (like semaphore
handling) to be non-interruptible to function properly.
This can be provided by inhibiting interrupts during the respective code sequence by
disabling and enabling them before and after the sequence.
The necessary overhead may be reduced by means of the ATOMIC instruction which allows
locking 1...4 instructions to an inseparable code sequence, during which the interrupt
system (standard interrupts and PEC requests) and Class A Traps (NMI
, stack
overflow/underflow) are disabled. A Class B Trap (such as illegal opcode or illegal bus
access), however, will interrupt the atomic sequence, since it indicates a severe hardware
problem.
The interrupt inhibit caused by an ATOMIC instruction gets active immediately, and no other
instruction will enter the pipeline except the one that follows the ATOMIC instruction, and no
interrupt request will be serviced in between.
All instructions requiring multiple cycles or hold states are regarded as one instruction in this
sense (example MUL is one instruction). Any instruction type can be used within an
inseparable code sequence.
27.9 Overriding the DPP addressing mechanism
The standard mechanism to access data locations uses one of the four data page pointers
(DPPx), which selects a 16 Kbytes data page, and a 14-bit offset within this data page. The
four DPPs allow immediate access to up to 64 Kbytes of data. In applications with big data
arrays, especially in HLL applications using large memory models, this may require frequent
reloading of the DPPs, even for single accesses.
The EXTP (extend page) instruction allows switching to an arbitrary data page for 1...4
instructions without having to change the current DPPs.
EXAMPLE: ATOMIC #3 ; The following 3 instructions are locked
; (No NOP required)
MOV R0, #1234H ; Instruction 1 (no other instr. enters the pipeline!)
MOV R1, #5678H ; Instruction 2
MUL R0, R1 ; Instruction 3: MUL regarded as one instruction
MOV R2, MDL
; This instruction is out of the scope of the ATOMIC
; instruction sequence
EXAMPLE: EXTP R15, #1 ; The override page number is stored in R15
MOV R0, [R14] ; The (14 Bit) page offset is stored in R14
MOV R1, [R13]
; This instruction uses the standard DPP
scheme!