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UM0404 High-speed synchronous serial interface
The data output pins MRST of all slave devices are connected together onto the one receive
line in this configuration. During a transfer each slave shifts out data from its shift register.
There are two ways to avoid collisions on the receive line due to different slave data:
Only one slave drives the line, it enables the driver of its MRST pin. All the other slaves
have to program there MRST pins to input. So only one slave can put its data onto the
master's receive line. Only receiving of data from the master is possible. The master selects
the slave device from which it expects data either by separate select lines, or by sending a
special command to this slave. The selected slave then switches its MRST line to output,
until it gets a de-selection signal or command.
The slaves use open drain output on MRST. This forms a AND-wired connection. The
receive line needs an external pull-up in this case. Corruption of the data on the receive line
sent by the selected slave is avoided, when all slaves which are not selected for
transmission to the master only send ones (‘1’). Since this high level is not actively driven
onto the line, but only held through the pull-up device, the selected slave can pull this line
actively to a low level when transmitting a zero bit. The master selects the slave device from
which it expects data either by separate select lines, or by sending a special command to
this slave.
After performing all necessary initialization of the SSC, the serial interfaces can be enabled.
For a master device, the alternate clock line will now go to its programmed polarity. The
alternate data line will go to either '0' or '1', until the first transfer will start. After a transfer the
alternate data line will always remain at the logic level of the last transmitted data bit.
When the serial interfaces are enabled, the master device can initiate the first data transfer
by writing the transmit data into register SSCTB. This value is copied into the shift register
(which is assumed to be empty at this time), and the selected first bit of the transmit data will
be placed onto the MTSR line on the next clock from the Baud rate generator (transmission
only starts, if SSCEN = ‘1’). Depending on the selected clock phase, also a clock pulse will
be generated on the SCLK line.
With the opposite clock edge the master at the same time latches and shifts in the data
detected at its input line MRST. This “exchanges” the transmit data with the receive data.
Since the clock line is connected to all slaves, their shift registers will be shifted
synchronously with the master's shift register, shifting out the data contained in the registers,
and shifting in the data detected at the input line. After the pre-programmed number of clock
pulses (via the data width selection) the data transmitted by the master is contained in all
slaves’ shift registers, while the master's shift register holds the data of the selected slave.
In the master and all slaves the content of the shift register is copied into the receive buffer
SSCRB and the receive interrupt flag SSCRIR is set.
A slave device will immediately output the selected first bit (MSB or LSB of the transfer data)
at pin MRST, when the content of the transmit buffer is copied into the slave's shift register.
It will not wait for the next clock from the Baud rate generator, as the master does. The
reason for this is that, depending on the selected clock phase, the first clock edge generated
by the master may be already used to clock in the first data bit. So the slave's first data bit
must already be valid at this time.
Note: A transmission and a reception takes place at the same time, regardless whether valid data
has been transmitted or received. This is different from asynchronous reception on ASC0.
The initialization of the SCLK pin on the master requires some attention in order to avoid
undesired clock transitions, which may disturb the other receivers. The state of the internal
alternate output lines is '1' as long as the SSC is disabled. This alternate output signal is
ANDed with the respective port line output latch. Enabling the SSC with an idle-low clock
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