High-speed synchronous serial interface UM0404
274/564 DocID13284 Rev 2
Note: The target of an access to SSCCON (control bit or flags) is determined by the state of
SSCEN prior to the access. Writing C057h to SSCCON in programming mode
(SSCEN = ‘0’) will initialize the SSC (SSCEN was ‘0’) and then turn it on (SSCEN = ‘1’).
When writing to SSCCON, make sure that reserved locations receive zeros.
The shift register of the SSC is connected to both the transmit pin and the receive pin via the
pin control logic (see Figure 112). Transmission and reception of serial data is synchronized
and takes place at the same time, so the same number of transmitted bit is also received.
Transmit data is written into the Transmit Buffer SSCTB. It is moved to the shift register as
soon as this is empty. An SSC-master (SSCMS = ‘1’) immediately begins transmitting, while
an SSC-slave (SSCMS = ‘0’) will wait for an active shift clock. When the transfer starts, the
busy flag SSCBSY is set and a transmit interrupt request (SSCTIR) will be generated to
indicate that SSCTB may be reloaded again. When the programmed number of bit (2...16)
has been transferred, the contents of the shift register are moved to the Receive Buffer
SSCRB and a receive interrupt request (SSCRIR) will be generated. If no further transfer is
to take place (SSCTB is empty), SSCBSY will be cleared at the same time. Software should
not modify SSCBSY, as this flag is hardware controlled. Only one SSC can be master at a
given time.
The transfer of serial data bit can be programmed in the following ways:
• The data width can be chosen from 2 bits to 16 bits.
• Transfer may start with the LSB or the MSB.
• The shift clock may be idle low or idle high.
• Data bit may be shifted with the leading or trailing edge of the clock signal.
• The Baud rate may be set for a range of values (refer to Section 12.3: Baud rate
generation on page 280 for the formula to calculate values or to the device datasheet
for specific values).
• The shift clock can be generated (master) or received (slave).
Bit Function (operating mode, SSCEN = ‘1’)
SSCBC
SSC bit Count Field
Shift counter is updated with every shifted bit. Do not write to
SSCTE
SSC Transmit Error Flag
1: Transfer starts with the slave’s transmit buffer not being updated
SSCRE
SSC Receive Error Flag
1: Reception completed before the receive buffer was read
SSCPE
SSC Phase Error Flag
1: Received data changes around sampling clock edge
SSCBE
SSC Baud rate Error Flag
1: More than factor 2 or 0.5 between Slave’s actual and expected Baud rate
SSCBSY SSC Busy Flag: Set while a transfer is in progress. Do not write to
SSCMS
SSC Master Select bit
0: Slave Mode. Operate on shift clock received via SCLK.
1: Master Mode. Generate shift clock and output it via SCLK.
SSCEN
SSC Enable bit = ‘1’
Transmission and reception enabled. Access to status flags and M/S control.
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