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UM0404 The general purpose timer units
Count direction control for auxiliary timer
The count direction of the auxiliary timer can be controlled in the same way as for the core
timer T6. The description and the table apply accordingly.
Timer T5 in timer mode or gated timer mode
When the auxiliary timer T5 is programmed to timer mode or gated timer mode, its operation
is the same as described for the core timer T6. The descriptions, figures and tables apply
accordingly with one exception: There is no output toggle latch and no alternate output pin
for T5.
Timer T5 in counter mode
Counter mode for the auxiliary timer T5 is selected by setting bit-field T5M in register
T5CON to ‘001b’. In counter mode timer T5 can be clocked either by a transition at the
external input pin T5IN, or by a transition of timer T6’s output toggle latch T6OTL.
The event causing an increment or decrement of the timer can be a positive, a negative, or
both a positive and a negative transition at either the input pin, or at the toggle latch T6OTL
Bit Function
T5I
Timer 5 Input Selection
Depends on the Operating Mode, see respective sections.
T5M
Timer 5 Mode Control (Basic Operating Mode)
0 0: Timer Mode
0 1: Counter Mode
1 0: Gated Timer with Gate active low
1 1: Gated Timer with Gate active high
T5R
Timer 5 Run bit
T5R = ‘0’: Timer / Counter 5 stops
T5R = ‘1’: Timer / Counter 5 runs
T5UD Timer 5 Up / Down Control
(1)
1. For the effects of bit TxUD and TxUDE refer to the direction Table 38.
T5UDE Timer 5 External Up/Down Enable
(1)
CT3
Capture Trigger 3
0: Inactive
1: Capture on Timer3 events
CI
Register CAPREL Input Selection
0 0: Capture disabled
0 1: Positive transition (rising edge) on CAPIN
1 0: Negative transition (falling edge) on CAPIN
1 1: Any transition (rising or falling edge) on CAPIN
T5CLR
Timer 5 Clear bit
T5CLR = ‘0’: Timer 5 not cleared on a capture
T5CLR = ‘1’: Timer 5 is cleared on a capture
T5SC
Timer 5 Capture Mode Enable
T5SC = ‘0’: Capture into register CAPREL Disabled
T5SC = ‘1’: Capture into register CAPREL Enabled
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