ST ST10F276E - Page 127

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UM0404 Interrupt and trap functions
All bits of XIR3SEL register are set by hardware when an interrupt is coming from the
peripheral, and/or by writing a logic ‘1’ in the corresponding bit of XIR3SET register.
All bits of XIR3SEL register are cleared by writing a logic ‘1’ in the corresponding bit of
XIR3CLR register. The register can anyway be also written directly by the software.
XIR3SET (EB42h) XBUS Reset Value: 0000h
XIR3CLR (EB44h) XBUS Reset Value: 0000h
IE.3
Interrupt Enable 3: XSSC Error
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.4
Interrupt Enable 4: XASC Error
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.5
Interrupt Enable 5: PLL Unlock / Oscillator Watchdog
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.6
Interrupt Enable 6: XPWM Channel 3...0
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.7 Interrupt Enable 7: No interrupt source associated.
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IESET[7:0] FLSET[7:0]
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Bit Function
FLSET.x
Interrupt Flag x SET (x=7...0)
Writing a ‘1’ will set the corresponding bit x in XIR3SEL register.
Writing a ‘0’ has no effect.
IESET.x
Interrupt Enable x SET (x=7...0)
Writing a ‘1’ will set the corresponding bit x in XIR3SEL register.
Writing a ‘0’ has no effect.
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IECLR[7:0] FLCLR[7:0]
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Bit Function