ST ST10F276E - Page 247

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UM0404 Asynchronous / synchronous serial interface
The operating mode of the serial channel ASC0 is controlled by its bit-addressable control
register S0CON. This register contains control bit for mode and error check selection, and
status flags for error identification.
S0CON (FFB0h / D8h) SFR Reset Value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S0R S0LB S0BRS S0ODD - S0OE S0FE S0PE S0OEN S0FEN S0PEN S0REN S0STP S0M
RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
S0M
ASC0 Mode Control
0 0 0: 8-bit data synchronous operation
0 0 1: 8-bit data asynchronous operation
0 1 0: Reserved. Do not use this combination
0 1 1: 7-bit data + parity asynchronous operation
1 0 0: 9-bit data asynchronous operation
1 0 1: 8-bit data + wake up bit asynchronous operation
1 1 0: Reserved. Do not use this combination
1 1 1: 8-bit data + parity asynchronous operation
S0STP
Number of Stop bit Selection asynchronous operation
0: One stop bit
1: Two stop bit
S0REN
Receiver Enable bit
0: Receiver disabled
1: Receiver enabled
(Reset by hardware after reception of byte in synchronous mode)
S0PEN
Parity Check Enable bit asynchronous operation
0: Ignore parity
1: Check parity
S0FEN
Framing Check Enable bit asynchronous operation
0: Ignore framing errors
1: Check framing errors
S0OEN
Overrun Check Enable bit
0: Ignore overrun errors
1: Check overrun errors
S0PE
Parity Error Flag
Set by hardware on a parity error (S0PEN
= ‘1’). Must be reset by software.
S0FE
Framing Error Flag
Set by hardware on a framing error (S0FEN
= ‘1’). Must be reset by software.
S0OE
Overrun Error Flag
Set by hardware on an overrun error (S0OEN
= ‘1’). Must be reset by software.
S0ODD
Parity Selection bit
0: Even parity (parity bit set on odd number of ‘1’s in data)
1: Odd parity (parity bit set on even number of ‘1’s in data)
S0BRS
Baud rate Selection bit
0: Divide clock by reload-value + constant (depending on mode)
1: Additionally reduce serial clock to 2/3rd