DocID13284 Rev 2 505/564
UM0404 Power reduction modes
Note: Leaving the main voltage regulator active during Power Down may lead to unexpected
behavior (ex: CPU wake-up) and power consumption higher than what specified.
XMISC (EB46h) XBUS Reset Value: 0000h
The ST10F276 provides two different operating Power Down modes:
• Protected Power Down mode,
• Interruptible Power Down mode.
The Power Down operating mode is selected by the bit PWDCFG in SYSCON register.
SYSCON (FF12h / 89h) SFR Reset Value: 0xx0h
Reset Value: 0000 0xx0 x000 0000b
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
–
VREG
OFF
CAN
CK2
CAN
PA R
ADC
MUX
– RWRWRWRW
Bit Function
ADCMUX
Port1L ADC Channels Enable
‘0’: Analog inputs on port P5.y can be converted (default configuration)
‘1’: Analog inputs on port P1.z can be converted. Only 8 channels can be managed
CANPAR
CAN Parallel Mode Selection
‘0’:CAN2 is mapped on P4.4/P4.7, while CAN1 is mapped on P4.5/P4.6
‘1’:CAN1 and CAN2 are mapped in parallel on P4.5/P4.6. This is effective only if
both CAN1 and
CAN2 are enabled through setting of bits CAN1EN and CAN2EN in XPERCON
register.
If CAN1 is disabled, CAN2 remains on P4.4/P4.7 even if bit CANPAR is set.
CANCK2
CAN Clock divider by 2 disable
‘0’:Clock provided to CAN modules is CPU clock divided by 2 (mandatory when
f
CPU
is higher
than 40 MHz)
‘1’: Clock provided to CAN modules is directly CPU clock
VREGOFF
Main Voltage Regulator disable for Power Down mode
‘0’: Default value after reset and when Power Down is not used.
‘1’: On-chip Main Regulator is turned off when Power Down mode is entered.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKSZ
ROM
S1
SGT
DIS
ROM
EN
BYT
DIS
CLK
EN
WR
CFG
CS
CFG
PWD
CFG
OWD
DIS
BDR
STEN
XPEN
VISI
BLE
XPER-
SHARE
RW RW RW RW RW RW RW RW RW RW RW RW RW RW
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