The central processing unit (CPU) UM0404
74/564 DocID13284 Rev 2
CP (FE10h / 08h) SFR Reset Value:FC00h
It is the user's responsibility to ensure that the physical GPR address, specified via the CP
register plus the short GPR address, must always be an IRAM location. If this condition is
not met, unexpected results may occur.
• Do not set CP below the IRAM start address, 00’F600h (2 Kbytes).
• Do not set CP above 00’FDFEh.
• Be careful using the upper GPRs with CP above 00’FDE0h.
The CP register can be updated via any instruction which is capable of modifying an SFR.
Note: Due to the internal instruction pipeline, a new CP value is not yet usable for GPR address
calculations of the instruction immediately following the instruction updating the CP register.
The Switch Context instruction (SCXT) makes it possible to save the content of register CP
on the stack and updating it with a new value in just one instruction cycle.
Several addressing modes use register CP implicitly for address calculations.
Short 4-bit GPR addresses (mnemonic: Rw or Rb) specify an address relative to the
memory location specified by the contents of the CP register, which is the base of the
current register bank.
Depending on whether a relative word (Rw) or byte (Rb) GPR address is specified, the short
4-bit GPR address is either multiplied by two or not before it is added to the content of
register CP (see Figure 15 on page 75).
Thus, both byte and word GPR accesses are possible in this way. GPRs used as indirect
address pointers are always accessed word wise.
For some instructions only the first four GPRs can be used as indirect address pointers.
These GPRs are specified via short 2-bit GPR addresses. The respective physical address
calculation is identical to that for the short 4-bit GPR addresses.
Short 8-bit register addresses (mnemonic: reg or bitoff) within a range from F0h to FFh
interpret the four least significant bits as short 4-bit GPR address, while the four most
significant bits are ignored.
The respective physical GPR address calculation is identical to that for the short 4-bit GPR
addresses. For single bit accesses on a GPR, the GPR's word address is calculated as just
described, but the position of the bits within the word is specified by a separate additional 4-
bit value.
1514131211109876543210
1111 CP 0
RRRR RW
R
Bit Function
CP
Modifiable portion of register CP
Specifies the (word) base address of the current register bank. When writing a value
to register CP with bit CP.11...CP.9 = ‘000’, bit CP.11...CP.10 are set to ‘11’ by
hardware, in all other cases all bits of bit-field “CP” receive the written value.
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