ST ST10F276E - Page 93

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UM0404 Multiply-accumulate unit (MAC)
MCW (FFDCh / EEh) SFR Reset Value: 0000h
MRW (FFDAh / EDh) SFR Reset Value: 0000h
Note: As for the CPU Core SFRs, any write operation with the regular instruction set to a single
byte of a MAC SFR clears the non-addressed complementary byte within the specified SFR.
Non-implemented SFR bits cannot be modified and will always supply a read value of ‘0’.
These registers are mapped in the SFR space and can be addressed by the regular
instruction set like any SFR. As mentioned previously, they can also be addressed by the
new instruction CoSTORE. This instruction allows the user to access the MAC registers
without any pipeline side effect. CoSTORE uses a specific 5-bit addressing mode called
CoReg. The following table gives the address of the MAC registers in this CoReg
addressing mode.
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MIE LM EM VM CM MP MS -
RW RW RW RW RW RW RW
Bit Function
MS
Saturation Mode
When set, enables automatic 32-bit saturation of the result of a MAC operation.
MP
Product Shift Mode
When set, enables the one-bit left shift of the multiplier output in case of a signed-
signed multiplication.
CM
C Mask
When set, the C Flag can generate a MAC interrupt request.
VM
SV Mask
When set, the SV Flag can generate a MAC interrupt request.
EM
E Mask
When set, the E Flag can generate a MAC interrupt request.
LM
SL Mask
When set, the SL Flag can generate a MAC interrupt request.
MIE
MAC Interrupt Enable
‘0’: MAC interrupt globally disabled.
‘1’: MAC interrupt globally enabled.
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MR - - Repeat Count
RW RW
Bit Function
Repeat Count
13-bit unsigned integer value
Indicates the number of time minus one a repeated instruction must be executed.
MR
Repeat Flag
Set when a repeated instruction is executed.