ST ST10F276E - Page 120

Interrupt and trap functions UM0404
120/564 DocID13284 Rev 2
All bits of XIR0SEL register are set by hardware when an interrupt is coming from the
peripheral, and/or by writing a logic ‘1’ in the corresponding bit of XIR0SET register.
All bits of XIR0SEL register are cleared by writing a logic ‘1’ in the corresponding bit of
XIR0CLR register. The register can anyway be also written directly by the software.
XIR0SET (EB12h) XBUS Reset Value: 0000h
IE.1
Interrupt Enable 1: I2C Transmit
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.2
Interrupt Enable 2: I2C Receive
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.3
Interrupt Enable 3: XSSC Transmit
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.4
Interrupt Enable 4: XSSC Receive
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.5
Interrupt Enable 5: XASC Transmit Buffer
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.6
Interrupt Enable 6: XASC Transmit
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.7
Interrupt Enable 7: XASC Receive
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
1514131211109876543210
IESET[7:0] FLSET[7:0]
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Bit Function
FLSET.x
Interrupt Flag x SET (x=7...0)
Writing a ‘1’ will set the corresponding bit x in XIR0SEL register.
Writing a ‘0’ has no effect.
IESET.x
Interrupt Enable x SET (x=7...0)
Writing a ‘1’ will set the corresponding bit x in XIR0SEL register.
Writing a ‘0’ has no effect.
Bit Function