ST ST10F276E - Page 121

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UM0404 Interrupt and trap functions
XIR0CLR (EB14h) XBUS Reset Value: 0000h
To enable the interrupt in the interrupt controller, the Interrupt Control Register XP0IC has to
be initialized. The associated interrupt vector is called XP0INT located at address 100h (trap
number 40h).
XP0IC (F186h / C3h) ESFR Reset Value: - - 00h
Note: Refer to Section 5.1.3: Interrupt control registers on page 100 for an explanation of the
control fields.
XIR1SEL (EB20h) XBUS Reset Value: 0000h
1514131211109876543210
IECLR[7:0] FLCLR[7:0]
WWWWWWWWWWWWWWWW
Bit Function
FLCLR.x
Interrupt Flag x CLEAR (x=7...0)
Writing a ‘1’ will clear the corresponding bit x in XIR0SEL register.
Writing a ‘0’ has no effect.
IECLR.x
Interrupt Enable x CLEAR (x=7...0)
Writing a ‘1’ will clear the corresponding bit x in XIR0SEL register.
Writing a ‘0’ has no effect.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
--------XP0IRXP0IE ILVL GLVL
RW RW RW RW
1514131211109876543210
IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 FL.7 FL.6 FL.5 FL.4 FL.3 FL.2 FL.1 FL.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
FL.0
Interrupt Flag 0: CAN2 Interrupt
‘0’: No interrupt request.
‘1’: Interrupt request pending.
FL.1
Interrupt Flag 1: I2C Transmit
‘0’: No interrupt request.
‘1’: Interrupt request pending.
FL.2
Interrupt Flag 2: I2C Receive
‘0’: No interrupt request.
‘1’: Interrupt request pending.
FL.3
Interrupt Flag 0: XSSC Transmit
‘0’: No interrupt request.
‘1’: Interrupt request pending.