ST ST10F276E - Page 122

Interrupt and trap functions UM0404
122/564 DocID13284 Rev 2
All bits of XIR1SEL register are set by hardware when an interrupt is coming from the
peripheral, and/or by writing a logic ‘1’ in the corresponding bit of XIR1SET register. All bits
of XIR1SEL register are cleared by writing a logic ‘1’ in the corresponding bit of XIR1CLR
register. The register can anyway be also written directly by the software.
FL.4
Interrupt Flag 4: XSSC Receive
‘0’: No interrupt request.
‘1’: Interrupt request pending.
FL.5
Interrupt Flag 5: XASC Transmit Buffer
‘0’: No interrupt request.
‘1’: Interrupt request pending.
FL.6
Interrupt Flag 6: XASC Transmit
‘0’: No interrupt request.
‘1’: Interrupt request pending.
FL.7
Interrupt Flag 7: XASC Receive
‘0’: No interrupt request.
‘1’: Interrupt request pending.
IE.0
Interrupt Enable 0: CAN2 Interrupt
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.1
Interrupt Enable 1: I2C Transmit
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.2
Interrupt Enable 2: I2C Receive
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.3
Interrupt Enable 3: XSSC Transmit
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.4
Interrupt Enable 4: XSSC Receive
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.5
Interrupt Enable 5: XASC Transmit Buffer
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.6
Interrupt Enable 6: XASC Transmit
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.7
Interrupt Enable 7: XASC Receive
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
Bit Function