ST ST10F276E - Page 125

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UM0404 Interrupt and trap functions
All bits of XIR2SEL register are set by hardware when an interrupt is coming from the
peripheral, and/or by writing a logic ‘1’ in the corresponding bit of XIR2SET register. All bits
of XIR2SEL register are cleared by writing a logic ‘1’ in the corresponding bit of XIR2CLR
register. The register can anyway be also written directly by the software.
XIR2SET (EB32h) XBUS Reset Value: 0000h
XIR2CLR (EB34h) XBUS Reset Value: 0000h
To enable the interrupt in the interrupt controller, the Interrupt Control Register XP2IC has to
be initialized. The associated interrupt vector is called XP2INT located at address 108h (trap
number 42h).
IE.6
Interrupt Enable 6: XASC Transmit
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
IE.7
Interrupt Enable 7: XASC Receive
‘0’: Interrupt request disabled.
‘1’: Interrupt request enabled.
1514131211109876543210
IESET[7:0] FLSET[7:0]
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Bit Function
FLSET.x
Interrupt Flag x SET (x=7...0)
Writing a ‘1’ will set the corresponding bit x in XIR2SEL register.
Writing a ‘0’ has no effect.
IESET.x
Interrupt Enable x SET (x=7...0)
Writing a ‘1’ will set the corresponding bit x in XIR2SEL register.
Writing a ‘0’ has no effect.
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IECLR[7:0] FLCLR[7:0]
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Bit Function
FLCLR.x
Interrupt Flag x CLEAR (x=7...0)
Writing a ‘1’ will clear the corresponding bit x in XIR2SEL register.
Writing a ‘0’ has no effect.
IECLR.x
Interrupt Enable x CLEAR (x=7...0)
Writing a ‘1’ will clear the corresponding bit x in XIR2SEL register.
Writing a ‘0’ has no effect.
Bit Function