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UM0404 XBUS high-speed synchronous serial interface
XSSCTB (E806h) XBUS Reset Value: 0000h
XSSCRB (E808h) XBUS Reset Value: xxxxh
It is moved to the shift register as soon as this is empty. An XSSC-master (SSCMS = ‘1’)
immediately begins transmitting, while an XSSC-slave (SSCMS = ‘0’) will wait for an active
shift clock. When the transfer starts, the busy flag SSCBSY is set and a transmit interrupt
request will be generated to indicate that XSSCTB may be reloaded again. When the
programmed number of bit (2...16) has been transferred, the contents of the shift register
are moved to the Receive Buffer XSSCRB and a receive interrupt request will be generated.
If no further transfer is to take place (XSSCTB is empty), SSCBSY will be cleared at the
same time. Software should not modify SSCBSY, as this flag is hardware controlled. Only
one XSSC can be master at a given time.
The transfer of serial data bit can be programmed in the following ways:
• The data width can be chosen from 2 bits to 16 bits.
• Transfer may start with the LSB or the MSB.
• The shift clock may be idle low or idle high.
• Data bit may be shifted with the leading or trailing edge of the clock signal.
• The Baud rate may be set for a range of values (refer to Section 12.3: Baud rate
generation on page 280 for the formula to calculate values or to the device datasheet
for specific values).
• The shift clock can be generated (master) or received (slave).
This allows the adaptation of the XSSC to a wide range of applications, where serial data
transfer is required.
The data width selection supports the transfer of frames of any length, from 2 bit
“characters” up to 16 bit “characters”. Starting with the LSB (SSCHB = ‘0’) allows
communication with ASC0 devices in synchronous mode like serial interfaces. Starting with
the MSB (SSCHB = ‘1’) allows operation compatible with the SPI interface.
Regardless which data width is selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right aligned in registers XSSCTB and XSSCRB, with the
LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for transfer
by the internal shift register logic. The unselected bits of XSSCTB are ignored, the
unselected bits of XSSCRB will be not valid and should be ignored by the receiver service
routine.
The clock control allows the adaptation of transmit and receive behavior of the XSSC to a
variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out transmit
data, while the other clock edge is used to latch in receive data. Bit SSCPH selects the
leading edge or the trailing edge for each function. Bit SSCPO selects the level of the clock
line in the idle state. So for an idle-high clock the leading edge is a falling one, a 1-to-0
transition. Figure 113 on page 276 is a summary.
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