ST ST10F276E - Page 431

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UM0404 CAN modules
IFx command mask registers
The control bits of the IFx Command Mask Register specify the transfer direction and select
which of the IFx Message Buffer Registers are source or target of the data transfer. The bits
of IFx Command Mask Register have different functions depending on the transfer direction
(Write or Read), defined through WR/RD bit of the register itself.
CAN1IF1CM (EF12h) XBUS Reset Value: 0000h
CAN2IF1CM (EE12h) XBUS Reset Value: 0000h
CAN1IF2CM (EF42h) XBUS Reset Value: 0000h
CAN2IF2CM (EE42h) XBUS Reset Value: 0000h
Direction Write:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
--------WR/RDMaskArbControl
ClrInt
Pnd
TxRqst/
NewDat
Data A Data B
RW RW RW RW RW RW RW RW
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
--------WR/RDMaskArbControl
ClrInt
Pnd
TxRqst/
NewDat
Data A Data B
RW RW RW RW RW RW RW RW
Bit Function
WR/RD
Write / Read
’0’: Read: Transfer data from the Message Object addressed by the Command
Request Register into the selected Message Buffer Registers.
’1’: Write: Transfer data from the selected Message Buffer Registers to the Message
Object addressed by the Command Request Register.
Bit Function
Data B
Access Data Bytes 4-7
’0’: Data Bytes 4-7 unchanged.
’1’: Transfer Data Bytes 4-7 to Message Object.
Data A
Access Data Bytes 0-3
’0’: Data Bytes 0-3 unchanged.
’1’: Transfer Data Bytes 0-3 to Message Object.
TxRqst/NewDat
Access Transmission Request Bit
’0’: TxRqst bit unchanged.
’1’: Set TxRqst bit.
Note: If a transmission is requested by programming bit TxRqst/NewDat in the
IFx Command Mask Register, bit TxRqst in the IFx Message Control Register will
be ignored.
ClrIntPnd
Clear Interrupt Pending Bit
When writing to a Message Object, this bit is ignored.