CAN modules UM0404
462/564 DocID13284 Rev 2
be defined for expandible CAN bus systems. The resulting time for Prop_Seg is converted
into time quanta (rounded up to the nearest integer multiple of t
q
).
The Sync_Seg is 1 t
q
long (fixed), leaving (bit time – Prop_Seg – 1) t
q
for the two Phase
Buffer Segments. If the number of remaining t
q
is even, the Phase Buffer Segments have
the same length, Phase_Seg2 = Phase_Seg1, else Phase_Seg2 = Phase_Seg1 + 1.
The minimum nominal length of Phase_Seg2 has to be regarded as well. Phase_Seg2 may
not be shorter than the CAN controller’s Information Processing Time, which is, depending
on the actual implementation, in the range of [0...2] t
q
.
The length of the Synchronization Jump Width is set to its maximum value, which is the
minimum of 4 and Phase_Seg1.
The oscillator tolerance range necessary for the resulting configuration is calculated by the
formulas given in System clock tolerance range on page 457.
If more than one configuration is possible, that configuration allowing the highest oscillator
or PLL tolerance range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same
bitrate. The calculation of the propagation time in the CAN network, based on the nodes
with the longest delay times, is done once for the whole network.
The CAN system’s oscillator (or PLL when used) tolerance range is limited by that node with
the lowest tolerance range.
The calculation may show that bus length or bitrate have to be decreased or that the
oscillator frequencies’ stability has to be increased in order to find a protocol compliant
configuration of the CAN bit timing.
The resulting configuration is written into the Bit Timing Register:
(Phase_Seg2 - 1) & (Phase_Seg1 + Prop_Seg - 1) & (SynchronizationJumpWidth - 1) &
(Prescaler - 1)
Example for bit timing at high baudrate
In this example, the CPU frequency (CAN module clock) is 10 MHz, BRP is 0, the bitrate is
1 Mbit/s.
t
q
100 ns = t
CPU
Delay of bus driver 50 ns
Delay of receiver circuit 30 ns
Delay of bus line (40m) 220 ns
t
Prop
600 ns = 6 x t
q
t
SJW
100 ns = 1 x t
q
t
PB1
100 ns = 1 x t
q
t
Seg1
= t
Prop
+ t
PB1
700 ns = 7 x t
q
t
Seg2
= t
PB2
200 ns = Information Processing Time + 1 x t
q
= 2 x t
q
t
Sync-Seg
100 ns = 1 x t
q
t
BT
1000 ns = t
Sync-Seg
+ t
Seg1
+ t
Seg2
= 10 x t
q
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