ST ST10F276E - Page 562

Revision history UM0404
562/564 DocID13284 Rev 2
19-Mar-2004 0.5
Figure 4 on page 41 and Figure 6 on page 45 updated: B0F6 into
B0F7.
XPER-SHARE Mode limits added in paragraph Section 2.4.1: XRAM
access via external masters on page 50.
Bit XPER-SHARE in SYSCON: description updated.
Note added in the paragraph Section 5.7: X-peripheral interrupt on
page 117.
Figure 74 on page 214 and Figure 75 on page 216 updated: B0F6
into B0F7.
Modified note for ADC minimum conversion time limitation - Note: on
page 382.
EML acronym replaced with extended format: Error Management
Logic in Section 21.7.1: Software initialization on page 418 and
Section : Status Register on page 425.
VREGOFF description updated.
Note about status of RTSIN
pin at Power-On added - Note: on page
474.
RP0H description updated (bit CLKCFG: PLL multiplication factors
x8 and x10 swapped).
Table Header updated replacing LP OSC with 32 kHz - Table 65 on
page 497.
Section 24.2: Power down mode on page 504: Voltage Regulator in
Power Down description updated.
32 kHz oscillator: removed low-power statement - Section 24.3:
Stand-by mode on page 509.
Low Power oscillator substituted with 32 kHz oscillator -
Section 24.3.2: Exiting stand-by mode on page 511.
PICON and XPICON registers added in the tables in Section 26:
Register set on page 515.
XPWMCON0SET/CLR and XPWMCON1SET/CLR register names
corrected at Section 26: Register set on page 515.
Note about bit addressability of Flash Control Registers updated in
Section 26.7: Flash registers ordered by name on page 541 and
Section 26.8: Flash registers ordered by address on page 541.
Section 27: System programming on page 545 updated replacing all
references to internal ROM with internal Flash, and external ROM
with external memory.
Table 77. Document revision history (continued)
Date Revision Changes