ST ST10F276E - Page 407

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UM0404 I
2
C interface
I2CCCR1 (EA06h) XBUS Reset Value: 0000h
I2COAR1 (EA08h) XBUS Reset Value: 0000h
7-bit addressing mode
AF
Acknowledge Failure
This bit is set by hardware when no acknowledge is returned. An interrupt is
generated if ITE
= 1. It is cleared by software by reading I2CSR2 register or by
hardware when the interface is disabled (PE
= 0).
The SCL line is not held low while AF
= 1.
‘0’: No acknowledge failure
‘1’: Acknowledge failure
ENDAD
End of address transmission
This bit is set by hardware when
- 7-bit addressing mode: the address byte has been transmitted;
- 10-bit addressing mode: the MSB and the LSB have been transmitted during the
addressing phase. When the master needs to receive data from the slave, it has to
send just the MSB of the slave once again; hence the ENDAD flag is set, without
waiting for the LSB of the address.
It is cleared by software by reading I2CSR2 and a following write to the I2CCR or by
hardware when the interface is disabled (PE
= 0).
‘0’: No end of address transmission
‘1’: End of address transmission
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
– FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0
RW RW RW RW RW RW RW RW
Bit Function
CC(6:0)
12-bit clock divider
CC(6:0) bits along with CC(11:7) of the register I2CCCR2 select the speed of the
bus (f
SCL
) depending on the I
2
C mode. They are not cleared when the interface is
disabled (PE
= 0).
– Standard mode (FM/SM = 0): f
SCL
≤ 100 kHz
f
SCL
= f
CPU
/ (2 x CC(11:0) + 7)
– Fast mode (FM/SM
= 1): f
SCL
> 100 kHz
f
SCL
= f
CPU
/ (3 x CC(11:0) + 9)
Note: The programmed f
SCL
assumes no load on SCL and SDA lines.
FM/SL
Fast/Standard I
2
C Mode
This bit is set and cleared by software. It is not cleared when the interface is
disabled (PE
= 0).
‘0’: Standard I
2
C mode
‘1’: Fast I
2
C mode
1514131211109876543210
– ADD7ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
RW RW RW RW RW RW RW RW
Bit Function