ST ST10F276E - Page 408

I
2
C interface UM0404
408/564 DocID13284 Rev 2
10-bit addressing mode
I2COAR2 (EA0Ah) XBUS Reset Value: 0000h
I2CDR (EA0Ch) XBUS Reset Value: 0000h
Bit Function
ADD0
Address direction bit
This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when
the interface is disabled (PE
= 0).
Note: Address 01h is always ignored.
ADD(7:1)
Interface address
These bits define the I
2
C bus address of the interface. They are not cleared when
the interface is disabled (PE
= 0).
Bit Function
ADD(7:0)
Interface address
These are the least significant bits of the I
2
C bus address of the interface. They are
not cleared when the interface is disabled (PE
= 0).
1514131211109876543210
– FR2 FR1 FR0 – ADD9 ADD8 –
RW RW RW RW RW
Bit Function
ADD(9:8)
Interface address
These are the most significant bits of the I
2
C bus address of the interface (10-bit
mode only). They are not cleared when the interface is disabled (PE
= 0).
FR(2:0)
Frequency Bits
These bits are set by software only when the interface is disabled (PE
= 0). To
configure the interface to I
2
C specified delays select the value corresponding to the
system frequency f
CPU
.
f
CPU
range (MHz) FR2 FR1 FR0
3.3 - 10.0 0 0 0
10.0 - 16.7 0 0 1
16.7 - 26.7 0 1 0
26.7 - 40.0 0 1 1
40.0 - 53.3 1 0 0
53.3 - 66.0 1 0 1
66.0 - 80.0 1 1 0
80.0 - 100.0 1 1 1
1514131211109876543210
– D7D6D5D4D3D2D1D0
RW RW RW RW RW RW RW RW