Cmsemicon CMS32L051 - Condition before the Clock Oscillation Stops

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CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
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4.6.7 Condition before the clock oscillation stops
The register flag settings and conditions before stopping clock oscillation (invalid external clock input) are
as follows.
Table 4-8 Conditions and flag settings before clock oscillation stops
clock
Conditions before the clock stops (invalid external clock input)
The flag setting of the
SFR register
High-speed internal
oscillator clock
MCS=1 or CLS=1
(The CPU runs on a clock other than the high-speed internal oscillator
clock).
HIOSTOP=1
X1 clock
MCS=0 or CLS=1
(The CPU runs on a clock other than the high-speed system clock).
MSTOP=1
External master system
clock
XT1 clock
CLS=0
(The CPU runs on a clock other than the secondary system clock).
XTSTOP=1
External subsystem
clock