Cmsemicon CMS32L051 - Serial Channel Stop Register M (Stm)

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CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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12.3.9 Serial channel stop register m (STm)
The STm register is a trigger register that sets the communication/stop count allowed for each channel.
If a "1" is written to each bit (STmn), the corresponding bit (SEmn) in the serial channel enable status
register m (SEm) is cleared to "0" (stop status). Since the STmn bit is a trigger bit, if the SEmn bit is "0", the
STmn bit is cleared immediately.
The STm register is set via a 16-bit memory operation command.
The low 8 bits of the STm register can be set with STmL and via 8-bit memory operation instructions.
After the reset signal is generated, the value of the STm register changes to 0000H.
Figure 12-13 Format of serial channel stop register m (STm)
Address: 40041124H (ST0) After reset: 0000HR/W
Symbol
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
ST0
Address: 40041564H (ST1) After reset: 0000HR/W
Symbol
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
ST1
STmn
Stop trigger for channel n operation
0
No triggering.
1
Clear the SEmn bit 0 to stop the communication from running.
Note The control register and shift register values, the SCLKmn pin and SDOmn pin, and the FEFmn flag, PEFmn flag, and
OVFmn flag hold status.
Note Bit15~4 of the ST0 register and bit15~2 of the ST1 register must be set to 0.
Note 1.m: unit number (m=0, 1) n: channel number (n=0~3).
2. The read value of the STm register is always 0000H.
0
0
0
0
0
0
0
0
0
0
0
0
ST03
ST02
ST01
ST00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ST11
ST10