CMS32L051 User Manual |Chapter 14 Serial interface IICA
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Figure 14-7 Format of IICA status register n (IICSn) (3/3)
Clear condition (ACKDn=0).
When a stop condition is detected
goes up
LRELn bit being 1 (exit
communication).
IICEn bit changes from 1 to 0 (stop
running).
9th clock rising
edge of the SCLAn line
Start detection of conditions
No start condition detected.
A start condition was detected, indicating that it was during address transfer.
Clear condition (STDn=0).
condition is detected
address is transferred
LRELn bit being 1 (exit
communication).
IICEn bit changes from 1 to 0 (stop
running).
etected
Detection of stop conditions
No stop condition detected.
A stop condition is detected, the master device ends communication and the bus is released.
Clear condition (SPDn=0).
set this bit, when the 1st clock of the address
transfer byte after detecting the start condition is
detected
WUPn bit changes from 1 to 0
IICEn bit changes from 1 to 0 (stop
running).
Note 1. LRELn: Bit6 of the IICA control register n0 (IICCTLn0).
IICEn: Bit7 of the IICA control register n0 (IICCTLn0).
2.n=0
14.3.4 IICA flag register n (IICFn)
This is the register that sets the I2C operating mode and represents the status of the I2C-bus.
The IICFn register is set via an 8-bit memory operation command. However, only the STTn clear flag
(STCFn) and the I2C-bus status flag (IICBSYn) can be read.
The communication reservation function is allowed or disallowed by the IICRSVn bit setting, and the initial
value of the IICBSYn bit is set by the STCENn bit. Only at bit7 (IICEn)=0) can only write IICRSVn bits and
STCENn bits. Only IICFn registers can be read after they are allowed to operate. After the reset signal is
generated, the value of this register becomes 00H.
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