CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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12.3.4 Serial communication operation setting register mn (SCRmn)
The SCRmn register is the communication operation setting register for channel n, which sets the data
transmit and receive modes, data and clock phases, whether to mask error signals, parity bits, start bits, stop
bits, and data length.
It is forbidden to overwrite the SCRmn register during operation (SEmn=1).
The SCRmn register is set via a 16-bit memory operation command.
After the reset signal is generated, the value of the SCRmn register changes to 0087H.
Figure 12-8 Format of serial communication operation setting register mn (SCRmn) (1/2)
Address: 40041118H(SCR00)~4004111EH(SCR03) After reset: 0087HR/W
40041558H(SCR10)~4004155AH(SCR13)
Symbol
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn
Setting of the channel n operating mode
Prohibited communication.
Enables transmit and receive.
SCLKp
SDOp
SDIp input timing
sequence
SCLKp
SDOp
SDIp input timing
sequence
SCLKp
SDOp
SDIp input timing
sequence
SCLKp
SDOp
SDIp input timing
sequence
data and clock phase selection in SSPI mode
in UART mode and simple I2C mode, must set DAPmn bit and CKPmn bit both to 0.
Type
Mask control of error interrupt signal (INTSREx (x=0 to 3))
Disable the generation of error interrupts INTSREx (generate INTSRx).
Enable error interrupt INTSREx (no INTSRx is generated when an error occurs).
The EOCmn bit must be set to "0" in SSPI mode and Simplified I
2
C mode or when sending from UART
Note 3
.
Note 1 Limited to SCR00, SCR02, SCR10 registers only.
2. Limited to SCR00 register and SCR01 register, the others are fixed as 1.
3. When the EOCmn bit is 0 and SSPImn is not used, it is possible to generate an error interrupt INTSREn.
Notice Bit 3, 6, and 11 must be set to "0" (also bit 5 of SCR01, SCR03, and SCR11 registers must be set to "0"), and bit 2
must be set to "1".
Remark m: Unit number (m=0, 1) n: channel number (n=0~3) p: SSPI number (p=00, 01, 10, 11, 20, 21)
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