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Cmsemicon CMS32L051 - Peripheral Enable Register 0 (PER0)

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V1.2.2
CMS32L051 User Manual |Chapter 7 Real-Time Clock
www.mcu.com.cn 223 / 703
7.3.1 Peripheral enable register 0 (PER0).
The PER0 register is the register that sets whether to enable or disable the supply of clocks to each
peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
To use a real-time clock, bit7 (RTCEN) must be set to 1. The PER0 register is set via an 8-bit
memory operation command. After the reset signal is generated, the value of this register becomes
00H.
Figure 7-2 Format of peripheral enable register 0 (PER0)
Address: 0x40020420
After reset:
00H
R/W
symbol
7
6
5
4
3
2
1
0
PER0
RTCEN
GODAEN
ADCEN
IICA0EN
SAU1EN
SAU0EN
TM41IN
TM40EN
RTCEN
Provides control of the real-time clock (RTC) and the input clock of a 15-bit interval timer
0
Stop supplying the input clock.
the real-time clock (RTC) and 15-bit interval timer.
-time clock (RTC) and 15-bit interval timer are in the reset state.
1
An input clock is provided.
-time clocks (RTCs) and 15-bit interval timers.
Note 1 If you want to use a real-time clock, you must first set the RTCEN bit to 1 in the stable oscillation of the count clock
(fRTC) and then set the following registers. When the RTCEN bit is 0, the write operation of the real-time clock
control register is ignored, and the read value is the initial value (except for the real-time clock selection register
(RTCCL), the port mode register, and the port register).
-time clock control register 0 (RTCC0).
-time clock control register 1 (RTCC1).
count register (SEC).
count register (MIN).
count register (HOUR).
count register (DAY).
count register (WEEK).

count register (YEAR).

clock minute register (ALARMWM).

).
2. By setting the RTCLPC bit of the subsystem clock supply mode control register (OSMC) to 1, the subsystem
clock can be stopped for peripheral functions other than the real-time clock and 15-bit interval timer in deep sleep
mode or sleep mode running on the subsystem clock.

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