CMS32L051 User Manual |Chapter 14 Serial interface IICA
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14.5.15 Other cautions
(1) When the STCENn bit is 0
After just allowing I
2
C to run (IICEn=1), it is considered a communication state (IICBSYn=1)
independent of the actual bus state. To communicate with the master without detecting a stop
condition, it is necessary to create a stop condition and communicate with the master after the
bus is released. For multi-master, master communication cannot occur in the state where the
bus is not released (no stop condition detected). Stop conditions are generated in the following
order:
(1) Set IICA control register n1 (IICCTLn1).
(2) Set bit7 (IICEn) of IICA control register n0 (IICCTLn0) to 1.
(3) Set bit0 (SPTn) of the IICCTLn0 register to 1.
(2) When the STCENn bit is 1
After I
2
C is just allowed to run (IICEn=1), it is considered a release state (IICBSYn=0)
regardless of the actual bus state. Therefore, when the first starting condition (STTn=1) is
generated, it is necessary to confirm that the bus has been released in order not to disrupt other
communications.
(3) When I
2
C communication is being made with other devices
When the SDAAn pin is low and the SCLAn pin is high, I
2
C macros are considered SDAAn
citations if I
2
C is allowed to run and participate in communication in the middle the foot changes
from high to low (start condition detected). If the value on the bus is recognized as an extension
code at this point, a reply is returned that interferes with I
2
C communication with other devices.
To avoid this, I
2
C must be started in the following order:
(1) Clear the bit4 (SPIEn) of the IICCTLn0 register to "0" to disable the generation of an interrupt
request signal (INTIICAn) when a stop condition is detected.
(2) Set bit7 (IICEn) of the IICCTLn0 register to 1 to allow I2C to run.
(3) Wait for the start condition to be detected.
(4) Before returning the answer (within 4 to 72 F
MCK
clocks after setting the IICEn bit to "1"), set
bit 6 (LRELn) of the IICCTLn0 register to "1" to force the detection to be disabled.
(4) After setting the STTn bit and SPTn bit (bit1 and bit0 of the IICCTLn0 register), the reset before
clearing "0" is prohibited.
(5) If a communication appointment is made, the SPIEn bit (bit 4 of the IICCTLn0 register) must be
set to "1" to generate an interrupt request when a stop condition is detected. After the interrupt
request is generated, the communication data is written to the IICA shift register n (IICAn) to start
the transmission. If no interrupt occurs when the stop condition is detected, the communication
stops in the wait state because no interrupt request is generated at the start of communication.
However, when the MSTSn bit (bit 7 of the IICA status register n(IICSn)) is detected by software,
it is not necessary to set the SPIEn bit to "1".
Remark n=0
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