Cmsemicon CMS32L051 - 9.4 Operation of clock output;buzzer controller; 9.5 Cautions for clock output;buzzer output control circuitry

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CMS32L051 User Manual |Chapter 9 Clock output/Buzzer Output Controller
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9.4 Operation of clock output/buzzer controller
It can be selected with 1 pin as clock output or buzzer output.
The CLKBUZ0 pin outputs the clock/buzzer selected by clock output select register 0 (CKS0).
The CLKBUZ1 pin outputs the clock/buzzer selected by clock output select register 1 (CKS1).
9.4.1 Operation of output pin
The CLKBUZn pin is output as follows:
1) Set the port multiplexing function configuration register (Pxx CFG), the port register (Pxx)
corresponding to the port that will be used as the CLKBUZ0 pin, and the port mode register (PMxx). and the
port mode control register (PMCxx) set to 0.
2) Select bit0~3 (CCSn0~CCSn2) of register (CKSn) through the clock output of CLKBUZn pin CSELn)
Select the output frequency (output is disabled).
3) Set bit7 (PCLOEn) of the CKSn register to 1 to allow clock/buzzer output.
Note 1 CLKBUZ1 fixed multiplexing to P15 port, with CLKBUZ1, there is no need to set the port multiplexing function
configuration register (Pxx CFG).
2. The control circuit used as the clock output starts or stops the clock output after one clock after the clock output
(PCLOEn bit) is allowed or disable. Pulses with narrow widths are not output at this time. The timing of the output and clock
output allowed or stopped by the PCLOEn bit is shown in Figure 9-3.
3.n=0, 1
Figure 9-3 Output timing of CLKBUZn pin
after 1 clock cycle
clock output
narrow pulses not recognized
9.5 Cautions for clock output/buzzer output control circuitry
When the main system clock is selected as the CLKBUZn output (CSELn=0), the output width of
CLKBUZn becomes narrower if it is shifted to deep sleep mode within 1.5 output clocks of the CLKBUZn pin
after setting the stop output (PCLOEn=0).