Cmsemicon CMS32L051 - Watchdog Timer Overflow Time Setting

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CMS32L051 User Manual |Chapter 10 Watchdog Timer
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10.4.2 Watchdog timer overflow time setting
Set the overflow time of the watchdog timer by option bytes (000C0H) bit3~1 (WDCS2~WDCS0).
In the event of an overflow, an internal reset signal is generated. If the window opens before the overflow
time, the allowed register for the watchdog timer is given
(WDTE) writes ACH, clears the count and restarts the count. The overflow times that can be set are
shown below.
Table 10-3 Watchdog timer overflow time settings
WDCS2
WDCS1
WDCS0
Overflow time of the watchdog timer
(f
IL
=20kHz (MAX.))
0
0
0
2
6
/f
IL
(3.2ms)
0
0
1
2
7
/f
IL
(6.4ms)
0
1
0
2
8
/f
IL
(12.8ms)
0
1
1
2
9
/f
IL
(25.6ms)
1
0
0
2
11
/f
IL
(102.4ms)
1
0
1
2
13
/fIL(409.6ms)
1
1
0
2
14
/f
IL
(819.2ms)
1
1
1
2
16
/f
IL
(3276.8ms)
Note f
IL:
Clock frequency of the low-speed internal oscillator