Cmsemicon CMS32L051 - Serial Flag Clear Trigger Register Mn (Sirmn)

V1.2.2
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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12.3.6 Serial flag clear trigger register mn (SIRmn)
This is the trigger register used to clear each error flag of channel n.
If you set the various (FECTmn, PECTmn, OVCTmn) to 1, the corresponding bits (FEFmn, PEFmn,
OVFmn) clear 0. Because the SDIRmn register is a trigger register, if the corresponding bit of the SSRmn
register is cleared, the SDIRmn register is also cleared immediately.
The SIRmn register is set via 16-bit memory operation instructions.
The low 8 bits of the SIRmn register can be set with SIRmnL and via 8-bit memory operation instructions.
After the reset signal is generated, the value of the SIRmn register changes to 0000H.
Figure 12-10 Format of serial flag clear trigger register mn (SIRmn)
Address: 40041108H(SIR00)~4004110EH(SIR03) After reset: 0000HR/W
40041548H(SIR10)~4004154AH(SIR11)
Symbol
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIRmn
FECTmn
Note
1
Channel n-frame error flag clear trigger
0
No clearance.
1
Clear the FEFMN bit of the SSRmn register to 0.
PECTmn
Channel n parity error flag clear trigger
0
No clearance.
1
Clear the PEFmn bit of the SS
OVCTmn
Channel n overflow error flag clear trigger
0
No clearance.
1
Clear the OVFmn bit of th
Note 1: Restricted to SIR01, SIR03, SIR11 registers only.
Notice Bit 15 to 3 (bit 15 to 2 for SIR00, SIR02 and SIR10 registers) must be set to "0".
Note 1.m: Unit number (m=0, 1) n: channel number (n=0~3).
2. Read value of the SIRmn register is always 0000H.
0
0
0
0
0
0
0
0
0
0
0
0
0
FECT
Mn
Note1
PEC
Tmn
OVC
Tmn