CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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5.5.2 Start timing of counter
The timer count register mn (TCRmn) enters the operating enable state by placing the TSmn
position bit of the timer channel start register m (TSm).
The operation from the counting enabled state to the start of the timer count register mn (TCRmn) is
shown in Table 5-5.
Table5-5 Operation from the counting enabled state to the start of the timer count register mn (TCRmn)
Operating mode of the timer
Operation after setting the TSmn bit to 1
No action is taken from the time the start trigger is detected (TSmn=1) until the
count clock is generated.
The value of the TDRmn register is loaded into the TCRmn register by the first
count clock and the count is decremented by the subsequent count clock (see
Operation in 5.5.3(1) Interval Timer Mode ).
Load the value of the TDRmn register into the TCRmn register by writing 1 to the
TSmn bit.
If the input edge of TImn is detected, the count is decremented by the subsequent
count clock. (Refer to 5.5.3(2) Operation of Event Counter Mode).
No action is taken from the time the start of the trigger is detected until the count
clock is generated.
The 0000H is loaded into the TCRmn register by the first count clock and the
count is incremented by the subsequent count clock (refer to the operation of the
capture mode 5.5.3(3) (interval measurement of the input pulse).
By writing 1 to the TSmn bit in the state where the timer is stopped (TEmn=0), it
enters the start trigger, etc
No action is taken from the time the start of the trigger is detected until the count
clock is generated.
The value of the TDRmn register is loaded into the TCRmn register by the first count
clock and passed through subsequent meters
The number of clocks is decremented (see 5.5.3(4) Single-Count Mode Operation).
Capture & Single Count Mode
By writing 1 to the TSmn bit in the state where the timer is stopped (TEmn=0), it
enters the start trigger, etc
No action is taken from the time the start of the trigger is detected until the count
clock is generated.
0000H is loaded into the TCRmn register by the first count clock and proceeded
via subsequent count clocks
Increment count (see 5.5.3(5) Capture & Operation of Single Count Mode
(Measurement of High Level Width)).
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