5.8.6 Operation as delay counter
The decreasing count can be started by a valid edge detection (external event) at the TImn pin input and
the INTTMmn is generated at any set interval (Timer interrupt).
During the period when the TEmn bit is 1, it is possible to set the TSmn bit to 1 by software to
start decreasing the count and generate INTTMmn (timer interrupt) at any set interval.
The interrupt generation period can be calculated using the following equation:
In single-count mode, the timer count register mn (TCRmn) is used as a decrement counter.
If the channel start trigger bits (TSmn, TSHm1, TSHm3) of the Timer Channel Start Register m (TSm) are set
to 1, the TEmn bit, TEHm1 bit and TEHm3 bit becomes 1 and enters the valid edge detection wait state of
the TImn pin. The valid edge detection by the TImn pin input starts the operation of the TCRmn register and
loads the value of the Timer Data Register mn (TDRmn). The TCRmn register starts counting decreasingly
from the value of the loaded TDRmn register by counting the clock. If TCRmn changes to 0000H, INTTMmn
is output and counting stops before a valid edge is detected for the next TImn pin input.
TDRmn registers can be overridden at any time, and the values of the overridden TDRmn registers are
valid from the next cycle.
Figure 5-58 Example of basic timing of operation as a delay counter
TSmn
TEmn
TImn
TCRmn
TDRmn
INTTMmn
Note 1. m: unit number (m= 0,1) n: channel number (n=0 ~ 3).
2. TSmn: Bit n of the timer channel start register m (TSm).
TEmn : Bit n of timer channel enable status register m (TEm).
TImn : TImn pin input signal
TCRmn: Timer counter register mn (TCRmn).
TDRmn: Timer data register mn (TDRmn).
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