Cmsemicon CMS32L051 - 8.3 Registers for controlling 15-bit interval timer

V1.2.2
CMS32L051 User Manual |Chapter 8 15-Bit Interval Timer
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8.3 Registers for controlling 15-bit interval timer
The 15-bit interval timer is controlled by the following registers.
 Peripheral enable register 0 (PER0).
 Real-time clock selection register (RTCCL).
 15-bit interval timer control register (ITMC)
8.3.1 Peripheral enable register 0 (PER0).
The PER0 register is a register that sets the clock to be allowed or disallowed to be supplied to
each peripheral hardware. Reduce power consumption and noise by stopping clocking unused
hardware.
To use a 15-bit interval timer, bit7 (RTCEN) must be set to 1. The PER0 register is set via an 8-
bit memory operation command. After the reset signal is generated, the value of this register becomes
00H.
Figure 8-2 Format of peripheral enable register 0 (PER0)
Address: 0x40020420
After reset: 00H
R/W
symbol
7
6
5
4
3
2
1
0
PER0
RTCEN
GODAEN
ADCEN
IICA0EN
SCI1EN
SCI0EN
TM41IN
TM40EN
RTCEN
Provides control of the real-time clock (RTC) and the input clock of a 15-bit interval timer
0
Stop supplying the input clock.
-time clock (RTC) and 15-bit interval timer.
-time clock (RTC) and 15-bit interval timer are in a reset state.
1
An input clock is provided.
-time clock (RTC) and 15-bit interval timer.